1. Field of the Invention
The embodiments of the present invention relate to a technology for liquid crystal display, and to a gate drive device for the liquid crystal display.
2. Discussion of the Background
A gate drive device of the liquid crystal display for providing a drive signal for a gate line includes multiple stages of shift register units. FIG. 1a is an illustrative diagram of a structure of the gate drive device of the liquid crystal display in the prior art. FIG. 1b is a timing diagram of the shift register units in the prior art. In said structure, each stage of the shift register unit (Shift Register, SR) includes a high voltage signal input terminal (VDDIN), a low voltage signal input terminal (VSSIN), a first clock signal input terminal (CLKIN), a second clock signal input terminal (CLKBIN), a gate drive signal output terminal (OUT), a signal input terminal (INPUT) and a reset signal input terminal (RESETIN). Except for the first stage of shift register unit (SR1) and the last stage of shift register unit (SRn+1), the gate drive signal output terminal for each stage of shift register unit is connected to the reset signal input terminal for a i-th stage of shift register unit adjacent thereto and the signal input terminal for a (i+1)-th stage of shift register unit adjacent thereto, a frame start signal (STV) is inputted from the signal input terminal (INPUT) of the first stage of shift register unit, the signal output terminal (OUTn+1) of the last stage of the shift register unit (SRn+1) is connected to the reset signal input terminal (RESETIN) of the i-th stage of shift register unit (SRn) adjacent thereto as well as the reset signal input terminal (RESETIN) thereof. The signal output terminal for each stage of the shift register unit is connected to a gate line (GL), for providing a gate drive signal for the gate line. The high voltage signal input terminal (VDDIN) of each stage of the shift register unit is connected to a high voltage signal line A where a high voltage signal (VDD) is inputted; the low voltage signal input terminal (VSSIN) is connected to a low voltage signal line B where a low voltage signal (VSS) is inputted; the first clock signal input terminal (CLKIN) is connected to a first clock signal line C where a first clock signal (CLK) is inputted; the second clock signal input terminal (CLKBIN) is connected to a second clock signal line D where a second clock signal (CLKB) is inputted.
In FIG. 1b, the signal output terminal (OUT) of each stage of the shift register unit outputs a high level every period of a frame, thereby controlling the thin film transistor (TFT) of the corresponding row to be turned on, such that progressive scanning of the liquid crystal display is implemented. The high level outputted from the last stage of the shift register unit (SRn+1) is used as the reset signal for both of itself and the previous stage of the shift register unit (SRn). In the prior art, the delay of the gate drive signal is large. FIG. 1c is a comparative diagram of the gate drive signal outputted from the signal output terminal (OUTn) of FIG. 1b versus the second clock signal. It can be seen from the FIG. 1c, there is a large delay between the rising edge of the gate drive signal outputted from the signal output terminal (OUTn) of the n-th stage of the shift register unit (SRn) and the rising edge of the second clock signal (CLKB), wherein td is a timing difference between the 50% of the rising edge of the second clock signal (CLKB) and the 50% of the rising edge of the gate drive signal outputted from the signal output terminal (OUTn). Also, in the prior art, each signal output terminal is directly discharged to a low level after being charged to a high level by a power supply, thus the charged and discharged amounts are large, and the high level signal outputted from the each signal output terminal is not sufficiently utilized which causes the power consumption of the gate drive device to be large.